{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8484529","patent":{"patent_number":"US-8484529","title":"Error correction and detection in a redundant memory system","assignee":null,"inventors":[],"filing_date":"2010-06-24T00:00:00.000Z","publication_date":"2013-07-09T00:00:00.000Z","cpc_codes":["G06F","G06F"],"num_claims":20,"abstract":"Error correction and detection in a redundant memory system that includes a memory controller; a plurality of memory channels in communication with the memory controller, the memory channels including a plurality of memory devices; a cyclical redundancy code (CRC) mechanism for detecting that one of the memory channels has failed, and for marking the memory channel as a failing memory channel; and an error correction code (ECC) mechanism. The ECC is configured for ignoring the marked memory channel and for detecting and correcting additional memory device failures on memory devices located on one or more of the other memory channels, thereby allowing the memory system to continue to run unimpaired in the presence of the memory channel failure."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Error correction and detection in a redundant memory system","description":"Error correction and detection in a redundant memory system that includes a memory controller; a plurality of memory channels in communication with the memory controller, the memory channels including","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8484529","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8484529","citation_suggestion":"Patentable. \"Error correction and detection in a redundant memory system\" (US-8484529). https://patentable.app/patents/US-8484529","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8484529","json":"https://patentable.app/api/llm-context/US-8484529","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T20:57:06.044Z"}