{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8484601","patent":{"patent_number":"US-8484601","title":"Optimizing cell libraries for integrated circuit design","assignee":null,"inventors":[],"filing_date":"2011-08-05T00:00:00.000Z","publication_date":"2013-07-09T00:00:00.000Z","cpc_codes":["G06F"],"num_claims":6,"abstract":"A method co-optimizes a design and a library in such a way to choose the best set of cells to implement the design. The method takes into account the idea of limiting the number of new cells while reducing target costs and respecting design constraints. The method chooses a minimum nearly optimum set of cells to optimize a design. This involves the simultaneous optimization of a cell-based design and a cell library used to implement it. The invention can produce only an optimized library for a specific application, when the circuit is disregarded. The method takes into account a set of new cells described as finalized cells or as virtual cells, possibly having different transistor topologies, different sizes, different logic functions, and/or different cell template than the original library."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Optimizing cell libraries for integrated circuit design","description":"A method co-optimizes a design and a library in such a way to choose the best set of cells to implement the design. The method takes into account the idea of limiting the number of new cells while red","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8484601","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8484601","citation_suggestion":"Patentable. \"Optimizing cell libraries for integrated circuit design\" (US-8484601). https://patentable.app/patents/US-8484601","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8484601","json":"https://patentable.app/api/llm-context/US-8484601","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T20:57:21.514Z"}