{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8489823","patent":{"patent_number":"US-8489823","title":"Efficient data prefetching in the presence of load hits","assignee":null,"inventors":[],"filing_date":"2012-06-27T00:00:00.000Z","publication_date":"2013-07-16T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F"],"num_claims":10,"abstract":"A microprocessor configured to access an external memory includes a first-level cache, a second-level cache, and a bus interface unit (BIU) configured to interface the first-level and second-level caches to a bus used to access the external memory. The BIU is configured to prioritize requests from the first-level cache above requests from the second-level cache. The second-level cache is configured to generate a first request to the BIU to fetch a cache line from the external memory. The second-level cache is also configured to detect that the first-level cache has subsequently generated a second request to the second-level cache for the same cache line. The second-level cache is also configured to request the BIU to refrain from performing a transaction on the bus to fulfill the first request if the BIU has not yet been granted ownership of the bus to fulfill the first request."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Efficient data prefetching in the presence of load hits","description":"A microprocessor configured to access an external memory includes a first-level cache, a second-level cache, and a bus interface unit (BIU) configured to interface the first-level and second-level cac","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8489823","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8489823","citation_suggestion":"Patentable. \"Efficient data prefetching in the presence of load hits\" (US-8489823). https://patentable.app/patents/US-8489823","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8489823","json":"https://patentable.app/api/llm-context/US-8489823","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T00:16:50.600Z"}