{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8490042","patent":{"patent_number":"US-8490042","title":"Performing routing optimization during circuit design","assignee":null,"inventors":[],"filing_date":"2009-10-29T00:00:00.000Z","publication_date":"2013-07-16T00:00:00.000Z","cpc_codes":["G06F","G06F"],"num_claims":21,"abstract":"One embodiment of the present invention provides a system that concurrently optimizes multiple routing objectives during routing of an integrated circuit (IC) chip design. During operation, the system starts by receiving a routing solution for the IC chip design and a set of routing objectives. The system then partitions the IC chip design into a set of partitions. Next, for each partition in the set of partitions, the system optimizes the routing solution by, iteratively: (1) analyzing the routing solution to determine weights for the set of routing objectives; (2) constructing a cost function based on the weights for the set of routing objectives; and (3) modifying the routing solution within the partition to attempt to optimize the cost function."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Performing routing optimization during circuit design","description":"One embodiment of the present invention provides a system that concurrently optimizes multiple routing objectives during routing of an integrated circuit (IC) chip design. During operation, the system","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8490042","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8490042","citation_suggestion":"Patentable. \"Performing routing optimization during circuit design\" (US-8490042). https://patentable.app/patents/US-8490042","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8490042","json":"https://patentable.app/api/llm-context/US-8490042","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T19:50:14.637Z"}