{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8490107","patent":{"patent_number":"US-8490107","title":"Processing resource allocation within an integrated circuit supporting transaction requests of different priority levels","assignee":null,"inventors":[],"filing_date":"2011-08-08T00:00:00.000Z","publication_date":"2013-07-16T00:00:00.000Z","cpc_codes":["H04L","H04L","H04L"],"num_claims":22,"abstract":"An integrated circuit 2 includes a plurality of transaction sources 6, 8, 10, 12, 14, 16, 18, 20 communicating via a ring-based interconnect 30 with shared caches 22, 24 each having an associated POC/POS 30, 34 and serving as a request servicing circuit. The request servicing circuits have a set of processing resources 36 that may be allocated to different transactions. These processing resources may be allocated either dynamically or statically. Static allocation can be made in dependence upon a selection algorithm. This selection algorithm may use a quality of service value/priority level as one of its input variables. A starvation ratio may also be defined such that lower priority levels are forced to be selected if they are starved of allocation for too long. A programmable mapping may be made between quality of service values and priority levels. The maximum number of processing resources allocated to each priority level may also be programmed."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Processing resource allocation within an integrated circuit supporting transaction requests of different priority levels","description":"An integrated circuit 2 includes a plurality of transaction sources 6, 8, 10, 12, 14, 16, 18, 20 communicating via a ring-based interconnect 30 with shared caches 22, 24 each having an associated POC/","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8490107","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8490107","citation_suggestion":"Patentable. \"Processing resource allocation within an integrated circuit supporting transaction requests of different priority levels\" (US-8490107). https://patentable.app/patents/US-8490107","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8490107","json":"https://patentable.app/api/llm-context/US-8490107","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T08:35:03.932Z"}