{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8490244","patent":{"patent_number":"US-8490244","title":"Methodologies for automatic 3-D device structure synthesis from circuit layouts for device simulation","assignee":null,"inventors":[],"filing_date":"2012-04-16T00:00:00.000Z","publication_date":"2013-07-23T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F"],"num_claims":13,"abstract":"A method of automatically generating structure files employing a full structure generator automated program is provided. An annotated device layout file is generated from a design layout by annotating the codes for design shapes with additional text representing the functionality of a physical structure associated with each design shape. Functioning individual semiconductor devices are identified from the annotated device layout file, and a circuit area including multiple interconnected semiconductor devices are identified. A front-end-of-line (FEOL) device structure file and a back-end-of-line (BEOL) device structure file are generated from layer by layer analysis of the components of the annotated device layout within the circuit area. Finite element meshes (FEMs) are generated for the FEOL and BEOL structure files and merged to provide a structure file that can be employed for simulation of semiconductor devices therein."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Methodologies for automatic 3-D device structure synthesis from circuit layouts for device simulation","description":"A method of automatically generating structure files employing a full structure generator automated program is provided. An annotated device layout file is generated from a design layout by annotating","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8490244","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8490244","citation_suggestion":"Patentable. \"Methodologies for automatic 3-D device structure synthesis from circuit layouts for device simulation\" (US-8490244). https://patentable.app/patents/US-8490244","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8490244","json":"https://patentable.app/api/llm-context/US-8490244","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T01:50:34.166Z"}