{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8492267","patent":{"patent_number":"US-8492267","title":"Pillar interconnect chip to package and global wiring structure","assignee":null,"inventors":[],"filing_date":"2012-10-02T00:00:00.000Z","publication_date":"2013-07-23T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":20,"abstract":"Pillar interconnect chip to package and global wiring structures and methods of manufacturing are discloses. The method includes forming a resist directly over at least one landing pad and at least one wiring layer, and forming a first pattern in the resist over the landing pad and a second pattern over the wiring layer, using a single lithography step. The method further includes forming metal in the first pattern in electrical contact with the landing pad. The method further includes removing remaining resist over the wiring layer to deepen the second pattern. The method further includes forming a pillar interconnect in the first pattern and a wiring in the second pattern by adding additional metal on the metal in the first pattern and over the at least one wiring layer in the second pattern, respectively. The method further includes removing any remaining resist."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Pillar interconnect chip to package and global wiring structure","description":"Pillar interconnect chip to package and global wiring structures and methods of manufacturing are discloses. The method includes forming a resist directly over at least one landing pad and at least on","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8492267","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8492267","citation_suggestion":"Patentable. \"Pillar interconnect chip to package and global wiring structure\" (US-8492267). https://patentable.app/patents/US-8492267","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8492267","json":"https://patentable.app/api/llm-context/US-8492267","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T16:46:35.519Z"}