{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8492279","patent":{"patent_number":"US-8492279","title":"Method of controlling critical dimensions of vias in a metallization system of a semiconductor device during silicon-ARC etch","assignee":null,"inventors":[],"filing_date":"2011-06-21T00:00:00.000Z","publication_date":"2013-07-23T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L"],"num_claims":20,"abstract":"When forming via openings in sophisticated semiconductor devices, a silicon-containing anti-reflective coating (ARC) layer may be efficiently used for adjusting the critical dimension of the via openings by using a two-step etch process in which, in at least one of the process steps, the flow rate of a reactive gas component may be controlled to increase or reduce the resulting width of an opening in the silicon ARC layer. In this manner, the spread of critical dimensions of vias around the target value may be significantly reduced while also reducing any maintenance and rework efforts."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method of controlling critical dimensions of vias in a metallization system of a semiconductor device during silicon-ARC etch","description":"When forming via openings in sophisticated semiconductor devices, a silicon-containing anti-reflective coating (ARC) layer may be efficiently used for adjusting the critical dimension of the via openi","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8492279","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8492279","citation_suggestion":"Patentable. \"Method of controlling critical dimensions of vias in a metallization system of a semiconductor device during silicon-ARC etch\" (US-8492279). https://patentable.app/patents/US-8492279","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8492279","json":"https://patentable.app/api/llm-context/US-8492279","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T11:53:48.473Z"}