{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8492901","patent":{"patent_number":"US-8492901","title":"Metal oxide semiconductor (MOS)-compatible high-aspect ratio through-wafer vias and low-stress configuration thereof","assignee":null,"inventors":[],"filing_date":"2009-11-06T00:00:00.000Z","publication_date":"2013-07-23T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L"],"num_claims":26,"abstract":"A structure includes a wafer having a top wafer surface. The wafer defines an opening. The top wafer surface defines a first reference direction perpendicular to the top wafer surface. The wafer has a thickness in the first reference direction. The structure also includes a through-wafer via formed in the opening. The through-wafer via has a shape, when viewed in a plane perpendicular to the first reference direction and parallel to the top wafer surface, of at least one of a spiral and a C-shape. The through-wafer via has a height in the first reference direction essentially equal to the thickness of the wafer in the first reference direction. Manufacturing techniques are also disclosed."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Metal oxide semiconductor (MOS)-compatible high-aspect ratio through-wafer vias and low-stress configuration thereof","description":"A structure includes a wafer having a top wafer surface. The wafer defines an opening. The top wafer surface defines a first reference direction perpendicular to the top wafer surface. The wafer has a","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8492901","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8492901","citation_suggestion":"Patentable. \"Metal oxide semiconductor (MOS)-compatible high-aspect ratio through-wafer vias and low-stress configuration thereof\" (US-8492901). https://patentable.app/patents/US-8492901","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8492901","json":"https://patentable.app/api/llm-context/US-8492901","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T12:47:53.714Z"}