{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8493089","patent":{"patent_number":"US-8493089","title":"Programmable logic circuit using three-dimensional stacking techniques","assignee":null,"inventors":[],"filing_date":"2011-04-06T00:00:00.000Z","publication_date":"2013-07-23T00:00:00.000Z","cpc_codes":["G11C"],"num_claims":12,"abstract":"A configurable die stack arrangement including a first configurable integrated circuit die located on a first substrate. The first configurable integrated circuit die includes a first array and a first configuration memory management circuit that includes an interface to the first array. The first array includes a first logic element and a first configuration memory. The configurable die stack arrangement also includes a second configurable integrated circuit die located on a second substrate that is different than the first substrate. The second configurable integrated circuit die includes a second array and a second configuration memory management circuit that includes an interface to the second array. The second array includes a second logic element and a second configuration memory. A signal is coupled to the first configuration management circuit and to the second configuration management circuit, and the first configuration memory management circuit includes circuitry to control the signal."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Programmable logic circuit using three-dimensional stacking techniques","description":"A configurable die stack arrangement including a first configurable integrated circuit die located on a first substrate. The first configurable integrated circuit die includes a first array and a firs","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8493089","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8493089","citation_suggestion":"Patentable. \"Programmable logic circuit using three-dimensional stacking techniques\" (US-8493089). https://patentable.app/patents/US-8493089","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8493089","json":"https://patentable.app/api/llm-context/US-8493089","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T19:13:50.450Z"}