{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8493397","patent":{"patent_number":"US-8493397","title":"State machine control for a pipelined L2 cache to implement memory transfers for a video processor","assignee":null,"inventors":[],"filing_date":"2005-11-04T00:00:00.000Z","publication_date":"2013-07-23T00:00:00.000Z","cpc_codes":["G06T","G06F","G06F","G06F","G06F","G06F","G06T","G09G","H04N","H04N","H04N","H04N","H04N","H04N","H04N","H04N"],"num_claims":23,"abstract":"A method for using a state machine to control a pipelined L2 cache to implement memory transfers for a video processor. The method includes accessing a queue of read requests from a video processor, and tracking each of a plurality of cache lines stored within the cache using a least recently used variable. For each a cache line hit out of the plurality of cache lines and corresponding to one of the read requests, the least recently used variable is adjusted for a remainder of the plurality of cache lines. A replacement cache line is determined by examining the least recently used variables for each of the plurality of cache lines. For each cache line miss, a cache line slot corresponding to the replacement cache line is allocated to store a new cache line responsive to the cache line miss."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"State machine control for a pipelined L2 cache to implement memory transfers for a video processor","description":"A method for using a state machine to control a pipelined L2 cache to implement memory transfers for a video processor. The method includes accessing a queue of read requests from a video processor, a","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8493397","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8493397","citation_suggestion":"Patentable. \"State machine control for a pipelined L2 cache to implement memory transfers for a video processor\" (US-8493397). https://patentable.app/patents/US-8493397","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8493397","json":"https://patentable.app/api/llm-context/US-8493397","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T11:51:36.307Z"}