{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8493797","patent":{"patent_number":"US-8493797","title":"Memory system and method having volatile and non-volatile memory devices at same hierarchical level","assignee":null,"inventors":[],"filing_date":"2012-08-06T00:00:00.000Z","publication_date":"2013-07-23T00:00:00.000Z","cpc_codes":["G11B","G06F","G06F","G06F"],"num_claims":15,"abstract":"A processor-based system includes a processor coupled to core logic through a processor bus. This includes a dynamic random access memory (“DRAM”) memory buffer controller. The DRAM memory buffer controller is coupled through a memory bus to a plurality of a dynamic random access memory (“DRAM”) modules and a flash memory module, which are at the same hierarchical level from the processor. Each of the DRAM modules includes a memory buffer to the memory bus and to a plurality of dynamic random access memory devices. The flash memory module includes a flash memory buffer coupled to the memory bus and to at least one flash memory device. The flash memory buffer includes a DRAM-to-flash memory converter operable to convert the DRAM memory requests to flash memory requests, which are then applied to the flash memory device."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Memory system and method having volatile and non-volatile memory devices at same hierarchical level","description":"A processor-based system includes a processor coupled to core logic through a processor bus. This includes a dynamic random access memory (“DRAM”) memory buffer controller. The DRAM memory buffer cont","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8493797","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8493797","citation_suggestion":"Patentable. \"Memory system and method having volatile and non-volatile memory devices at same hierarchical level\" (US-8493797). https://patentable.app/patents/US-8493797","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8493797","json":"https://patentable.app/api/llm-context/US-8493797","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T14:05:22.607Z"}