{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8495310","patent":{"patent_number":"US-8495310","title":"Method and system including plural memory controllers and a memory access control bus for accessing a memory device","assignee":null,"inventors":[],"filing_date":"2008-09-22T00:00:00.000Z","publication_date":"2013-07-23T00:00:00.000Z","cpc_codes":["G06F","G06F"],"num_claims":28,"abstract":"A system and method utilize a memory device that may be accessed by a plurality of controllers or processor cores via respective ports of the memory device. Each controller may be coupled to a respective port of the memory device via a data bus. Each port of the memory device may be associated with a predefined section of memory, thereby giving each controller access to a distinct section of memory without interference from other controllers. A common command/address bus may couple the plurality of controllers to the memory device. Each controller may assert an active signal on a memory access control bus to gain access to the command/address bus to initiate a memory access. In some embodiments, a plurality of memory devices may be arranged in a memory package in a stacked die memory configuration."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method and system including plural memory controllers and a memory access control bus for accessing a memory device","description":"A system and method utilize a memory device that may be accessed by a plurality of controllers or processor cores via respective ports of the memory device. Each controller may be coupled to a respect","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8495310","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8495310","citation_suggestion":"Patentable. \"Method and system including plural memory controllers and a memory access control bus for accessing a memory device\" (US-8495310). https://patentable.app/patents/US-8495310","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8495310","json":"https://patentable.app/api/llm-context/US-8495310","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T11:19:54.123Z"}