{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8495436","patent":{"patent_number":"US-8495436","title":"System and method for memory testing in electronic circuits","assignee":null,"inventors":[],"filing_date":"2012-06-17T00:00:00.000Z","publication_date":"2013-07-23T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C"],"num_claims":18,"abstract":"An electronic circuit includes first and second circuits that include corresponding built-in-self-test (BIST) engines to perform memory testing operations on corresponding first and second memory block and generate first and second memory repair data. A multiplexer receives the first and second memory repair data and selectively transmits the first memory repair data during a first test cycle and the second memory repair data during a second test cycle. A shadow register buffers the first memory repair data during the first test cycle and a fuse processor sequentially receives and stores the first and second memory repair data during the second test cycle."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"System and method for memory testing in electronic circuits","description":"An electronic circuit includes first and second circuits that include corresponding built-in-self-test (BIST) engines to perform memory testing operations on corresponding first and second memory bloc","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8495436","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8495436","citation_suggestion":"Patentable. \"System and method for memory testing in electronic circuits\" (US-8495436). https://patentable.app/patents/US-8495436","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8495436","json":"https://patentable.app/api/llm-context/US-8495436","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T01:36:00.519Z"}