{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8497197","patent":{"patent_number":"US-8497197","title":"Method for manufacturing a high-performance semiconductor structure with a replacement gate process and a stress memorization technique","assignee":null,"inventors":[],"filing_date":"2010-09-26T00:00:00.000Z","publication_date":"2013-07-30T00:00:00.000Z","cpc_codes":["H01L"],"num_claims":11,"abstract":"A method for manufacturing a semiconductor structure includes providing an n-type field effect transistor comprising a source region, a drain region, and a first gate; forming a tensile stress layer on the n-type field effect transistor; removing the first gate so as to form a gate opening; performing an anneal so that the source region and the drain region memorize a stress induced by the tensile stress layer; forming a second gate; removing the tensile stress layer; and forming an interlayer dielectric layer on the n-type field effect transistor. A replacement process is combined with a stress memorization technique for enhancing the stress memorization effect and increasing mobility of electrons, which in turn improves overall properties of the semiconductor structure."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method for manufacturing a high-performance semiconductor structure with a replacement gate process and a stress memorization technique","description":"A method for manufacturing a semiconductor structure includes providing an n-type field effect transistor comprising a source region, a drain region, and a first gate; forming a tensile stress layer o","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8497197","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8497197","citation_suggestion":"Patentable. \"Method for manufacturing a high-performance semiconductor structure with a replacement gate process and a stress memorization technique\" (US-8497197). https://patentable.app/patents/US-8497197","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8497197","json":"https://patentable.app/api/llm-context/US-8497197","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T14:31:13.573Z"}