{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8497550","patent":{"patent_number":"US-8497550","title":"Multi-level DRAM cell using CHC technology","assignee":null,"inventors":[],"filing_date":"2011-03-14T00:00:00.000Z","publication_date":"2013-07-30T00:00:00.000Z","cpc_codes":["G11C","G11C"],"num_claims":3,"abstract":"A DRAM memory cell includes: a first finFET structure; and a second finFET structure adjacent to the first finFET structure. The second finFET structure includes: a source follower transistor in a first fin of the second finFET structure; an access transistor in a second fin of the second fin FET structure; a write word line; and a read word line stacked above the write word line. When the read word line is fired high, the source follower transistor enables data to be read from the first finFET structure."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Multi-level DRAM cell using CHC technology","description":"A DRAM memory cell includes: a first finFET structure; and a second finFET structure adjacent to the first finFET structure. The second finFET structure includes: a source follower transistor in a fir","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8497550","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8497550","citation_suggestion":"Patentable. \"Multi-level DRAM cell using CHC technology\" (US-8497550). https://patentable.app/patents/US-8497550","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8497550","json":"https://patentable.app/api/llm-context/US-8497550","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T03:36:25.008Z"}