{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8499207","patent":{"patent_number":"US-8499207","title":"Memory devices and method for error test, recordation and repair","assignee":null,"inventors":[],"filing_date":"2012-07-27T00:00:00.000Z","publication_date":"2013-07-30T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C"],"num_claims":24,"abstract":"In a memory device, an on-die register is provided that is configured to store a row address as well as a column address of a memory cell that fails a test. Storing the row address frees testing from being limited to activating at one time only rows related to a common redundant segment. Storing the row address also guides repair using segmented redundancy. As an addition or alternative, information may be stored in an anti-fuse bank that is designed to provide access to a redundant cell but has not yet enabled access to that cell. If the information stored in the anti-fuse bank relates to the failure of the redundant cell, such information may be used to avoid repairing with that redundant cell."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Memory devices and method for error test, recordation and repair","description":"In a memory device, an on-die register is provided that is configured to store a row address as well as a column address of a memory cell that fails a test. Storing the row address frees testing from ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8499207","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8499207","citation_suggestion":"Patentable. \"Memory devices and method for error test, recordation and repair\" (US-8499207). https://patentable.app/patents/US-8499207","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8499207","json":"https://patentable.app/api/llm-context/US-8499207","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T13:13:39.402Z"}