{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8501395","patent":{"patent_number":"US-8501395","title":"Line edge roughness reduction and double patterning","assignee":null,"inventors":[],"filing_date":"2008-06-03T00:00:00.000Z","publication_date":"2013-08-06T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L"],"num_claims":20,"abstract":"Embodiments of the present invention relate to lithographic processes used in integrated circuit fabrication for improving line edge roughness (LER) and reduced critical dimensions (CD) for lines and/or trenches. Embodiments use the combinations of polarized light lithography, shrink coating processes, and double exposure processes to produce synergetic effects in the formation of trench structures having good resolution, reduced CDs, reduced pitch, and reduced LER in the lines and/or trenches of the patterned interconnect structures."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Line edge roughness reduction and double patterning","description":"Embodiments of the present invention relate to lithographic processes used in integrated circuit fabrication for improving line edge roughness (LER) and reduced critical dimensions (CD) for lines and/","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8501395","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8501395","citation_suggestion":"Patentable. \"Line edge roughness reduction and double patterning\" (US-8501395). https://patentable.app/patents/US-8501395","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8501395","json":"https://patentable.app/api/llm-context/US-8501395","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T16:55:22.337Z"}