{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8502303","patent":{"patent_number":"US-8502303","title":"Semiconductor device","assignee":null,"inventors":[],"filing_date":"2010-05-26T00:00:00.000Z","publication_date":"2013-08-06T00:00:00.000Z","cpc_codes":["H01L"],"num_claims":8,"abstract":"Provided is a semiconductor device which is capable of preventing an increase in power consumption of an SGT, i.e., a three-dimensional semiconductor transistor, due to an increase in off-leak current. The semiconductor device comprises: a first-conductive type first silicon pillar: a first dielectric surrounding a side surface of the first silicon pillar; a gate surrounding the dielectric; a second silicon pillar provided underneath the first silicon pillar; and a third silicon pillar provided on a top of the first silicon pillar. The second silicon pillar has a second-conductive type high-concentration impurity region formed in a surface thereof except at least a part of a contact surface region with the first silicon pillar, and a first-conductive type impurity region formed therein and surrounded by the second-conductive type high-concentration impurity region. The third silicon pillar has a second-conductive type high-concentration impurity region formed in a surface thereof except at least a part of a contact surface region with the first silicon pillar, and a first-conductive type impurity region formed therein and surrounded by the second-conductive type high-concentration impurity region of the third silicon pillar. The first-conductive type impurity region of each of the second silicon pillar and the third silicon pillar has a length greater than that of a depletion layer extending from a base portion of the second-conductive type high-concentration impurity region of a respective one of the second silicon pillar and the third silicon pillar."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Semiconductor device","description":"Provided is a semiconductor device which is capable of preventing an increase in power consumption of an SGT, i.e., a three-dimensional semiconductor transistor, due to an increase in off-leak current","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8502303","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8502303","citation_suggestion":"Patentable. \"Semiconductor device\" (US-8502303). https://patentable.app/patents/US-8502303","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8502303","json":"https://patentable.app/api/llm-context/US-8502303","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T23:29:09.885Z"}