{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8502376","patent":{"patent_number":"US-8502376","title":"Wirebondless wafer level package with plated bumps and interconnects","assignee":null,"inventors":[],"filing_date":"2011-05-05T00:00:00.000Z","publication_date":"2013-08-06T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":28,"abstract":"A semiconductor package includes a carrier strip having a die cavity and bump cavities. A semiconductor die is mounted in the die cavity of the carrier strip. In one embodiment, the semiconductor die is mounted using a die attach adhesive. In one embodiment, a top surface of the first semiconductor die is approximately coplanar with a top surface of the carrier strip proximate to the die cavity. A metal layer is disposed over the carrier strip to form a package bump and a plated interconnect between the package bump and a contact pad of the first semiconductor die. An underfill material is disposed in the die cavity between the first semiconductor die and a surface of the die cavity. A passivation layer is disposed over the first semiconductor die and exposes a contact pad of the first semiconductor die. An encapsulant is disposed over the carrier strip."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Wirebondless wafer level package with plated bumps and interconnects","description":"A semiconductor package includes a carrier strip having a die cavity and bump cavities. A semiconductor die is mounted in the die cavity of the carrier strip. In one embodiment, the semiconductor die ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8502376","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8502376","citation_suggestion":"Patentable. \"Wirebondless wafer level package with plated bumps and interconnects\" (US-8502376). https://patentable.app/patents/US-8502376","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8502376","json":"https://patentable.app/api/llm-context/US-8502376","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T22:14:04.140Z"}