{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8504866","patent":{"patent_number":"US-8504866","title":"Supplying hysteresis effect mitigated clock signals based on silicon-test characterized parameter","assignee":null,"inventors":[],"filing_date":"2010-07-30T00:00:00.000Z","publication_date":"2013-08-06T00:00:00.000Z","cpc_codes":["G06F","G06F"],"num_claims":14,"abstract":"Embodiments of systems and methods are described for reducing the effects of hysteresis in the operation of data processing circuitry. In this embodiment of the invention, adaptive control circuitry is used to reduce the effects of hysteresis. The embodiment disclosed herein provides significant reduction in the effects of hysteresis and, therefore, a significant reduction in the amount of guard band needed to compensate for hysteresis effects in SOI processes and thereby improving the performance/power characteristics of the circuit."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Supplying hysteresis effect mitigated clock signals based on silicon-test characterized parameter","description":"Embodiments of systems and methods are described for reducing the effects of hysteresis in the operation of data processing circuitry. In this embodiment of the invention, adaptive control circuitry i","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8504866","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8504866","citation_suggestion":"Patentable. \"Supplying hysteresis effect mitigated clock signals based on silicon-test characterized parameter\" (US-8504866). https://patentable.app/patents/US-8504866","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8504866","json":"https://patentable.app/api/llm-context/US-8504866","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T13:41:21.294Z"}