{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8504884","patent":{"patent_number":"US-8504884","title":"Threshold voltage techniques for detecting an imminent read failure in a memory array","assignee":null,"inventors":[],"filing_date":"2009-10-29T00:00:00.000Z","publication_date":"2013-08-06T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C"],"num_claims":21,"abstract":"A technique for detecting an imminent read failure in a memory array includes determining whether a memory array, which does not exhibit an uncorrectable error correcting code (ECC) read during an initial array integrity check at a normal read verify voltage level, exhibits an uncorrectable ECC read during a subsequent array integrity check at a margin read verify voltage level. The technique also includes providing an indication of an imminent read failure for the memory array when the memory array exhibits an uncorrectable ECC read during the subsequent array integrity check. In this case, the margin read verify voltage level is different from the normal read verify voltage level."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Threshold voltage techniques for detecting an imminent read failure in a memory array","description":"A technique for detecting an imminent read failure in a memory array includes determining whether a memory array, which does not exhibit an uncorrectable error correcting code (ECC) read during an ini","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8504884","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8504884","citation_suggestion":"Patentable. \"Threshold voltage techniques for detecting an imminent read failure in a memory array\" (US-8504884). https://patentable.app/patents/US-8504884","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8504884","json":"https://patentable.app/api/llm-context/US-8504884","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T23:55:45.777Z"}