{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8504903","patent":{"patent_number":"US-8504903","title":"Data error check circuit, data error check method, data transmission method using data error check function, semiconductor memory apparatus and memory system using data error check function","assignee":null,"inventors":[],"filing_date":"2010-12-16T00:00:00.000Z","publication_date":"2013-08-06T00:00:00.000Z","cpc_codes":["G06F","G11C"],"num_claims":23,"abstract":"Various embodiments of a memory system are disclosed. In one exemplary embodiment, the memory system may include a semiconductor memory apparatus configured to generate error check signals in a column direction and a row direction of data groups to be transmitted through a plurality of data input/output terminals in a read operation and output the error check signals together with the data groups, and a memory controller configured to control data read/write operations of the semiconductor memory apparatus, generate error check signals by performing error check in a column direction and a row direction of data groups to be transmitted in a write operation, and provide the error check signals to the semiconductor memory apparatus together with the data groups."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Data error check circuit, data error check method, data transmission method using data error check function, semiconductor memory apparatus and memory system using data error check function","description":"Various embodiments of a memory system are disclosed. In one exemplary embodiment, the memory system may include a semiconductor memory apparatus configured to generate error check signals in a column","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8504903","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8504903","citation_suggestion":"Patentable. \"Data error check circuit, data error check method, data transmission method using data error check function, semiconductor memory apparatus and memory system using data error check function\" (US-8504903). https://patentable.app/patents/US-8504903","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8504903","json":"https://patentable.app/api/llm-context/US-8504903","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T19:51:42.535Z"}