{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8507375","patent":{"patent_number":"US-8507375","title":"Alignment tolerant semiconductor contact and method","assignee":null,"inventors":[],"filing_date":"2012-02-02T00:00:00.000Z","publication_date":"2013-08-13T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L"],"num_claims":16,"abstract":"An alignment tolerant electrical contact is formed by providing a substrate on which is a first electrically conductive region (e.g., a MOSFET gate) having an upper surface, the first electrically conductive region being laterally bounded by a first dielectric region, applying a mask having an opening extending partly over a contact region (e.g., for the MOSFET source or drain) on the substrate and over a part of the upper surface, forming a passage through the first dielectric region extending to the contact region and the part of the upper surface, thereby exposing the contact region and the part of the upper surface, converting the part of the upper surface to a second dielectric region and filling the opening with a conductor making electrical contact with the contact region but electrically insulated from the electrically conductive region by the second dielectric region."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Alignment tolerant semiconductor contact and method","description":"An alignment tolerant electrical contact is formed by providing a substrate on which is a first electrically conductive region (e.g., a MOSFET gate) having an upper surface, the first electrically con","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8507375","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8507375","citation_suggestion":"Patentable. \"Alignment tolerant semiconductor contact and method\" (US-8507375). https://patentable.app/patents/US-8507375","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8507375","json":"https://patentable.app/api/llm-context/US-8507375","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T06:58:28.971Z"}