{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8507994","patent":{"patent_number":"US-8507994","title":"Semiconductor device","assignee":null,"inventors":[],"filing_date":"2011-08-08T00:00:00.000Z","publication_date":"2013-08-13T00:00:00.000Z","cpc_codes":["G11C"],"num_claims":7,"abstract":"In a memory cell including CMOS inverters, an increase in an area of the memory cell caused by restrictions on a gate wiring due to a leakage current and restrictions due to design rules is suppressed. A first wiring and a second wiring are laid out as a first metal layer in the memory cell that includes a first inverter and a second inverter. The first wiring is connected with two drains in the first inverter and a second gate wiring in the second inverter. The second wiring is connected with two drains in the second inverter and a first gate wiring in the first inverter. The first wiring is laid out to overlap with the second gate wiring, and the second wiring is laid out to overlap with the first gate wiring. A second metal layer is laid out above the first metal layer, and a third metal layer is laid out above the second metal layer."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Semiconductor device","description":"In a memory cell including CMOS inverters, an increase in an area of the memory cell caused by restrictions on a gate wiring due to a leakage current and restrictions due to design rules is suppressed","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8507994","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8507994","citation_suggestion":"Patentable. \"Semiconductor device\" (US-8507994). https://patentable.app/patents/US-8507994","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8507994","json":"https://patentable.app/api/llm-context/US-8507994","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T23:28:44.724Z"}