{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8508255","patent":{"patent_number":"US-8508255","title":"Method and apparatus for reducing power consumption in a digital circuit by controlling the clock","assignee":null,"inventors":[],"filing_date":"2012-05-15T00:00:00.000Z","publication_date":"2013-08-13T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F"],"num_claims":27,"abstract":"A method and apparatus that controls the clock of a digital circuit, and therefore power consumption, without substantially comprising performance is provided. The apparatus may include monitoring the utilization of a First in First Out (FIFO) buffer. For example in a systems and methods according to the invention, clock speed may be reduced when the FIFO is relatively empty and increased when the FIFO is relatively full. The clock speed may be controlled by a phase locked loop, a clock divider, a clock masking device or a combination of more than one of these methods. Power reduction may also be obtained by controlling the clocking of different stages of a pipelined device. One or more aspects of the inventions may be implemented in combination with other aspects of the invention to further reduce power use."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method and apparatus for reducing power consumption in a digital circuit by controlling the clock","description":"A method and apparatus that controls the clock of a digital circuit, and therefore power consumption, without substantially comprising performance is provided. The apparatus may include monitoring the","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8508255","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8508255","citation_suggestion":"Patentable. \"Method and apparatus for reducing power consumption in a digital circuit by controlling the clock\" (US-8508255). https://patentable.app/patents/US-8508255","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8508255","json":"https://patentable.app/api/llm-context/US-8508255","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T08:35:31.412Z"}