{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8508993","patent":{"patent_number":"US-8508993","title":"Method and apparatus of performing an erase operation on a memory integrated circuit","assignee":null,"inventors":[],"filing_date":"2012-08-06T00:00:00.000Z","publication_date":"2013-08-13T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C"],"num_claims":9,"abstract":"Various discussed approaches improve the over erase issue and the coupling effect, and include (A) multilevel contacts between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line; (B) a sufficient separation distance between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line. These are examples of electrically isolating (i) the first outer selected word line of an erase group, from (ii) the first unselected word line outside the ease group neighboring the first outer selected word line."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method and apparatus of performing an erase operation on a memory integrated circuit","description":"Various discussed approaches improve the over erase issue and the coupling effect, and include (A) multilevel contacts between (i) the first outer selected word line of an erase group, and (ii) the fi","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8508993","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8508993","citation_suggestion":"Patentable. \"Method and apparatus of performing an erase operation on a memory integrated circuit\" (US-8508993). https://patentable.app/patents/US-8508993","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8508993","json":"https://patentable.app/api/llm-context/US-8508993","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T20:30:54.748Z"}