{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8510616","patent":{"patent_number":"US-8510616","title":"Scalable scan-based test architecture with reduced test time and test power","assignee":null,"inventors":[],"filing_date":"2008-02-14T00:00:00.000Z","publication_date":"2013-08-13T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C"],"num_claims":18,"abstract":"A scalable scan-based architecture with reduced test time, test power and test pin-count in scan based testing of ICs. In an embodiment, a test vector is scanned serially into a functional memory element at a first frequency, which then de-multiplexes the bits in the test vector to multiple sub-chains at a lower frequency. Due to the use of lower frequency to scan-in, the power dissipation is reduced. Due to the use of the higher frequency to scan-in the test vector as well as multiple sub-chains, the test time is reduced. Due to the use of the functional memory elements for scanning in the test vector at higher frequency, any number of chains can potentially be supported."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Scalable scan-based test architecture with reduced test time and test power","description":"A scalable scan-based architecture with reduced test time, test power and test pin-count in scan based testing of ICs. In an embodiment, a test vector is scanned serially into a functional memory elem","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8510616","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8510616","citation_suggestion":"Patentable. \"Scalable scan-based test architecture with reduced test time and test power\" (US-8510616). https://patentable.app/patents/US-8510616","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8510616","json":"https://patentable.app/api/llm-context/US-8510616","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T01:51:22.160Z"}