{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8510701","patent":{"patent_number":"US-8510701","title":"Over stress verify design rule check","assignee":null,"inventors":[],"filing_date":"2012-01-16T00:00:00.000Z","publication_date":"2013-08-13T00:00:00.000Z","cpc_codes":["G06F","G06F"],"num_claims":11,"abstract":"Some aspects of this disclosure provide for electronic design automation (EDA) techniques that check whether individual blocks, such as transistors or other semiconductor devices, are connected to their correct power domains during design. In this way, the disclosed EDA techniques can limit or prevent overstress conditions applied to blocks and help to improve reliability of integrated circuits, when manufactured."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Over stress verify design rule check","description":"Some aspects of this disclosure provide for electronic design automation (EDA) techniques that check whether individual blocks, such as transistors or other semiconductor devices, are connected to the","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8510701","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8510701","citation_suggestion":"Patentable. \"Over stress verify design rule check\" (US-8510701). https://patentable.app/patents/US-8510701","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8510701","json":"https://patentable.app/api/llm-context/US-8510701","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T18:51:27.632Z"}