{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8513103","patent":{"patent_number":"US-8513103","title":"Method for manufacturing vertical transistor having buried junction","assignee":null,"inventors":[],"filing_date":"2011-10-04T00:00:00.000Z","publication_date":"2013-08-20T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":29,"abstract":"A buried junction is formed in a vertical transistor of a semiconductor device. Wall bodies are formed from a semiconductor substrate, the wall bodies protruding while having a first side surface and a second side surface in the opposite side of the first side surface; forming a one side contact mask having an opening which selectively opens a portion of the first side surface of the wall body; and forming a first impurity layer and a second impurity layer surrounding the first impurity layer by diffusing impurities having different diffusivities into the portion of the first side surface exposed to the opening."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method for manufacturing vertical transistor having buried junction","description":"A buried junction is formed in a vertical transistor of a semiconductor device. Wall bodies are formed from a semiconductor substrate, the wall bodies protruding while having a first side surface and ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8513103","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8513103","citation_suggestion":"Patentable. \"Method for manufacturing vertical transistor having buried junction\" (US-8513103). https://patentable.app/patents/US-8513103","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8513103","json":"https://patentable.app/api/llm-context/US-8513103","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T09:16:12.564Z"}