{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8516292","patent":{"patent_number":"US-8516292","title":"Method and apparatus for providing symmetrical output data for a double data rate DRAM","assignee":null,"inventors":[],"filing_date":"2011-01-21T00:00:00.000Z","publication_date":"2013-08-20T00:00:00.000Z","cpc_codes":["G11C","G06F","G06F","G11C","G11C","G11C","G11C","G11C","G11C","G11C"],"num_claims":24,"abstract":"An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data signal or a timing signal, from a logic circuit, for example a memory device. A first phase detector, array of delay lock loop (DLL) delay elements and accompanying circuitry are disclosed to phase-lock the rising edge of the output signal with the rising edge of the system clock XCLK signal. Additionally, a comparator circuit, a register delay, an array of DLL delay elements and accompanying circuitry are disclosed to add or subtract delay from the falling edge of the DQ signal in order to produce a symmetrical output of the DQ signal."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method and apparatus for providing symmetrical output data for a double data rate DRAM","description":"An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data signal or a timing signal, from a logic","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8516292","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8516292","citation_suggestion":"Patentable. \"Method and apparatus for providing symmetrical output data for a double data rate DRAM\" (US-8516292). https://patentable.app/patents/US-8516292","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8516292","json":"https://patentable.app/api/llm-context/US-8516292","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T00:14:34.990Z"}