{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8519520","patent":{"patent_number":"US-8519520","title":"Semiconductor package of small footprint with a stack of lead frame die paddle sandwich between high-side and low-side MOSFETs and manufacturing method","assignee":null,"inventors":[],"filing_date":"2011-11-22T00:00:00.000Z","publication_date":"2013-08-27T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":11,"abstract":"A semiconductor package method for co-packaging high-side (HS) and low-side (LS) semiconductor chips is disclosed. The HS and LS semiconductor chips are attached to two opposite sides of a lead frame, with a bottom drain electrode of the LS chip connected to a top side of the lead frame and a top source electrode of the HS chip connected to a bottom side of the lead frame through a solder ball. The stacking configuration of HS chip, lead frame and LS chip reduces the package size. A bottom metal layer covering the bottom of HS chip exposed outside of the package body provides both electrical connection and thermal conduction."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Semiconductor package of small footprint with a stack of lead frame die paddle sandwich between high-side and low-side MOSFETs and manufacturing method","description":"A semiconductor package method for co-packaging high-side (HS) and low-side (LS) semiconductor chips is disclosed. The HS and LS semiconductor chips are attached to two opposite sides of a lead frame,","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8519520","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8519520","citation_suggestion":"Patentable. \"Semiconductor package of small footprint with a stack of lead frame die paddle sandwich between high-side and low-side MOSFETs and manufacturing method\" (US-8519520). https://patentable.app/patents/US-8519520","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8519520","json":"https://patentable.app/api/llm-context/US-8519520","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T05:38:00.423Z"}