{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8520453","patent":{"patent_number":"US-8520453","title":"Device for generating a test pattern of a memory chip and method thereof","assignee":null,"inventors":[],"filing_date":"2011-12-14T00:00:00.000Z","publication_date":"2013-08-27T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C"],"num_claims":15,"abstract":"A method of generating a test pattern of a memory chip includes generating and outputting a pattern enabling signal according to a first pattern signal and a second pattern signal, generating and outputting a first pre-input-output signal and a second pre-input-output signal according to a memory bank signal, a section signal, and the pattern enabling signal, executing an exclusive-OR logic operation on a third input-output signal and the second pattern signal to generate and output a first enabling signal, generating and outputting a first input-output signal and a second input-output signal according to the first enabling signal, the first pre-input-output signal and the second pre-input-output signal, and writing a predetermined logic voltage to each memory cell of the memory chip according to the first input-output signal and the second input-output signal."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Device for generating a test pattern of a memory chip and method thereof","description":"A method of generating a test pattern of a memory chip includes generating and outputting a pattern enabling signal according to a first pattern signal and a second pattern signal, generating and outp","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8520453","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8520453","citation_suggestion":"Patentable. \"Device for generating a test pattern of a memory chip and method thereof\" (US-8520453). https://patentable.app/patents/US-8520453","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8520453","json":"https://patentable.app/api/llm-context/US-8520453","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T14:59:24.131Z"}