{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8521994","patent":{"patent_number":"US-8521994","title":"Interleaving corresponding data elements from part of two source registers to destination register in processor operable to perform saturation","assignee":null,"inventors":[],"filing_date":"2010-12-22T00:00:00.000Z","publication_date":"2013-08-27T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F"],"num_claims":23,"abstract":"An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to pack the packed data responsive to a pack instruction received by the decoder. A first packed data element and a second packed data element are received from the first source register. A third packed data element and a fourth packed data element are received from the second source register. The circuit packs packing a portion of each of the packed data elements into a destination register resulting with the portion from second packed data element adjacent to the portion from the first packed data element, and the portion from the fourth packed data element adjacent to the portion from the third packed data element."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Interleaving corresponding data elements from part of two source registers to destination register in processor operable to perform saturation","description":"An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to pack the packed data respon","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8521994","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8521994","citation_suggestion":"Patentable. \"Interleaving corresponding data elements from part of two source registers to destination register in processor operable to perform saturation\" (US-8521994). https://patentable.app/patents/US-8521994","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8521994","json":"https://patentable.app/api/llm-context/US-8521994","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T15:00:05.972Z"}