{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8522126","patent":{"patent_number":"US-8522126","title":"Blocking memory readback in a programmable logic device","assignee":null,"inventors":[],"filing_date":"2010-12-22T00:00:00.000Z","publication_date":"2013-08-27T00:00:00.000Z","cpc_codes":["G06F"],"num_claims":11,"abstract":"A programmable logic device (PLD) is provided that includes: a configuration memory including a plurality of memory cells arranged according to rows and columns, wherein a subset of the rows are RAM rows, and wherein a subset of the columns in each RAM row are RAM columns and at least one column in each RAM row is a flag bit column, the memory cells corresponding to the flag bit column and RAM rows operable to store flag bit signals; a soft error detection (SED) circuit operable to read the configuration memory to derive a checksum; a logic circuit to determine if a RAM row is being read by the SED circuit that includes an asserted flag bit; and a blocking circuit that provides a known logical value to the SED circuit responsive to the logic circuit to block readback of the memory cells corresponding to the RAM rows and RAM columns."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Blocking memory readback in a programmable logic device","description":"A programmable logic device (PLD) is provided that includes: a configuration memory including a plurality of memory cells arranged according to rows and columns, wherein a subset of the rows are RAM r","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8522126","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8522126","citation_suggestion":"Patentable. \"Blocking memory readback in a programmable logic device\" (US-8522126). https://patentable.app/patents/US-8522126","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8522126","json":"https://patentable.app/api/llm-context/US-8522126","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T11:13:43.059Z"}