{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8522178","patent":{"patent_number":"US-8522178","title":"Re-modeling a memory array for accurate timing analysis","assignee":null,"inventors":[],"filing_date":"2011-09-07T00:00:00.000Z","publication_date":"2013-08-27T00:00:00.000Z","cpc_codes":["G06F","G06F"],"num_claims":23,"abstract":"A system and method for analyzing the timing requirements of a memory array are disclosed. The memory cell circuitry used in the original memory array may utilize two bi-directional passgate transistors which are both used during read and write operations on the memory cell, e.g., where signals can flow across the passgate transistors in two directions. A model of the memory array may be created according to a memory cell model that uses uni-directional passgate transistors. Modeling the memory array with uni-directional circuitry may enable a static timing analysis tool to determine the critical path through the memory array. Once the critical path has been determined from the model of the memory array, a dynamic simulation of the critical path in the original memory array may be performed to accurately determine the timing requirements of the original memory array."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Re-modeling a memory array for accurate timing analysis","description":"A system and method for analyzing the timing requirements of a memory array are disclosed. The memory cell circuitry used in the original memory array may utilize two bi-directional passgate transisto","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8522178","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8522178","citation_suggestion":"Patentable. \"Re-modeling a memory array for accurate timing analysis\" (US-8522178). https://patentable.app/patents/US-8522178","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8522178","json":"https://patentable.app/api/llm-context/US-8522178","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T19:33:56.886Z"}