{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8522244","patent":{"patent_number":"US-8522244","title":"Method and apparatus for scheduling for multiple memory controllers","assignee":null,"inventors":[],"filing_date":"2010-05-07T00:00:00.000Z","publication_date":"2013-08-27T00:00:00.000Z","cpc_codes":["G06F"],"num_claims":20,"abstract":"In at least one embodiment, a method includes locally scheduling a memory request requested by a thread of a plurality of threads executing on at least one processor. The memory request is locally scheduled according to a quality-of-service priority of the thread. The quality-of-service priority of the thread is based on a quality of service indicator for the thread and system-wide memory bandwidth usage information for the thread. In at least one embodiment, the method includes determining the system-wide memory bandwidth usage information for the thread based on local memory bandwidth usage information associated with the thread periodically collected from a plurality of memory controllers during a timeframe. In at least one embodiment, the method includes at each mini-timeframe of the timeframe accumulating the system-wide memory bandwidth usage information for the thread and updating the quality-of-service priority based on the accumulated system-wide memory bandwidth usage information for the thread."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method and apparatus for scheduling for multiple memory controllers","description":"In at least one embodiment, a method includes locally scheduling a memory request requested by a thread of a plurality of threads executing on at least one processor. The memory request is locally sch","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8522244","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8522244","citation_suggestion":"Patentable. \"Method and apparatus for scheduling for multiple memory controllers\" (US-8522244). https://patentable.app/patents/US-8522244","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8522244","json":"https://patentable.app/api/llm-context/US-8522244","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T18:03:44.715Z"}