{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8524569","patent":{"patent_number":"US-8524569","title":"Methods of forming an isolation layer and methods of manufacturing semiconductor devices having an isolation layer","assignee":null,"inventors":[],"filing_date":"2011-05-17T00:00:00.000Z","publication_date":"2013-09-03T00:00:00.000Z","cpc_codes":["H01L"],"num_claims":14,"abstract":"In a method of forming an isolation layer, first and second trenches are formed on a substrate. The first and the second trenches have first and second widths, respectively, and the second width is greater than the first width. A second isolation layer pattern partially fills the second trench. A first isolation layer pattern and the third isolation layer pattern are formed. The first isolation layer pattern fills the first trench, and the third isolation layer pattern is formed on the second isolation layer pattern and fills a remaining portion of the second trench."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Methods of forming an isolation layer and methods of manufacturing semiconductor devices having an isolation layer","description":"In a method of forming an isolation layer, first and second trenches are formed on a substrate. The first and the second trenches have first and second widths, respectively, and the second width is gr","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8524569","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8524569","citation_suggestion":"Patentable. \"Methods of forming an isolation layer and methods of manufacturing semiconductor devices having an isolation layer\" (US-8524569). https://patentable.app/patents/US-8524569","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8524569","json":"https://patentable.app/api/llm-context/US-8524569","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T16:37:59.537Z"}