{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8525245","patent":{"patent_number":"US-8525245","title":"eDRAM having dynamic retention and performance tradeoff","assignee":null,"inventors":[],"filing_date":"2011-04-21T00:00:00.000Z","publication_date":"2013-09-03T00:00:00.000Z","cpc_codes":["H01L"],"num_claims":9,"abstract":"A semiconductor chip has an embedded dynamic random access memory (eDRAM) in an independently voltage controlled silicon region that is a circuit element useful for controlling capacitor values of eDRAM deep trench capacitors and threshold voltages of field effect transistors overlying the independently voltage controlled silicon region. Retention time and performance of the eDRAM is controlled by applying a voltage to the independently voltage controlled silicon region."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"eDRAM having dynamic retention and performance tradeoff","description":"A semiconductor chip has an embedded dynamic random access memory (eDRAM) in an independently voltage controlled silicon region that is a circuit element useful for controlling capacitor values of eDR","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8525245","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8525245","citation_suggestion":"Patentable. \"eDRAM having dynamic retention and performance tradeoff\" (US-8525245). https://patentable.app/patents/US-8525245","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8525245","json":"https://patentable.app/api/llm-context/US-8525245","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T05:11:55.432Z"}