{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8525569","patent":{"patent_number":"US-8525569","title":"Synchronizing global clocks in 3D stacks of integrated circuits by shorting the clock network","assignee":null,"inventors":[],"filing_date":"2011-08-25T00:00:00.000Z","publication_date":"2013-09-03T00:00:00.000Z","cpc_codes":["G06F","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":25,"abstract":"There is provided a clock distribution network for synchronizing global clock signals within a 3D chip stack having two or more strata. On each of the two or more strata, the clock distribution network includes a clock grid having a plurality of sectors for providing the global clock signals to various chip locations, a multiple-level buffered clock tree for driving the clock grid and including at least a root and a plurality of clock buffers, and one or more multiplexers for providing the global clock signals to at least a portion of the buffered clock tree. Inputs of at least some of the plurality of clock buffers on each of the two or more strata are shorted together using chip-to-chip interconnects to reduce skewing of the global clock signals with respect to the various chip locations."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Synchronizing global clocks in 3D stacks of integrated circuits by shorting the clock network","description":"There is provided a clock distribution network for synchronizing global clock signals within a 3D chip stack having two or more strata. On each of the two or more strata, the clock distribution networ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8525569","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8525569","citation_suggestion":"Patentable. \"Synchronizing global clocks in 3D stacks of integrated circuits by shorting the clock network\" (US-8525569). https://patentable.app/patents/US-8525569","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8525569","json":"https://patentable.app/api/llm-context/US-8525569","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T22:12:08.332Z"}