{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8526250","patent":{"patent_number":"US-8526250","title":"Address delay circuit of semiconductor memory apparatus","assignee":null,"inventors":[],"filing_date":"2011-08-27T00:00:00.000Z","publication_date":"2013-09-03T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C"],"num_claims":16,"abstract":"An address delay circuit of a semiconductor memory apparatus includes a first group control pulse generation unit configured to generate a first control pulse after input of a first group column address strobe pulse and passage of a time corresponding to a first set multiple of one cycle of a clock, a second group control pulse generation unit configured to generate a second control pulse after input of a second group column strobe address pulse and passage of a time corresponding to a second set multiple of the one cycle of the clock, a first address storage unit configured to receive and store a first group external address in response to the first control pulse, and output a first group internal address, and a second address storage unit configured to receive and store a second group external address in response to the second control pulse, and output a second group internal address."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Address delay circuit of semiconductor memory apparatus","description":"An address delay circuit of a semiconductor memory apparatus includes a first group control pulse generation unit configured to generate a first control pulse after input of a first group column addre","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8526250","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8526250","citation_suggestion":"Patentable. \"Address delay circuit of semiconductor memory apparatus\" (US-8526250). https://patentable.app/patents/US-8526250","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8526250","json":"https://patentable.app/api/llm-context/US-8526250","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T20:58:19.407Z"}