{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8527736","patent":{"patent_number":"US-8527736","title":"Systems and methods for improving address translation speed","assignee":null,"inventors":[],"filing_date":"2010-09-07T00:00:00.000Z","publication_date":"2013-09-03T00:00:00.000Z","cpc_codes":["G06F","G06F"],"num_claims":11,"abstract":"A computer system has a translation lookaside buffer (TLB) having a plurality of entries for mapping virtual memory addresses to physical memory addresses and logic configured to perform the following steps for an entry of the TLB: (a) selecting a TLB entry size for the entry; (b) determining whether a mapping for the entry is aligned with a boundary of a contiguous section of memory without overshooting an end of the contiguous section of memory, wherein the mapping is based on the TLB entry size and maps virtual memory addresses to physical memory addresses for a section of the memory consistent with the TLB entry size; (c) if the mapping is determined to be aligned with the boundary of the contiguous section of memory without overshooting the end of the contiguous section of memory, configuring the entry with the mapping written into the entry; and (d) repeating steps (a) through (c) until a mapping is found to be aligned with the boundary of the contiguous section of memory without overshooting the end of the contiguous section of memory, wherein the logic is configured to repeat steps (a) through (d) until the contiguous section of memory is entirely mapped to virtual addresses by entries of the TLB."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Systems and methods for improving address translation speed","description":"A computer system has a translation lookaside buffer (TLB) having a plurality of entries for mapping virtual memory addresses to physical memory addresses and logic configured to perform the following","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8527736","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8527736","citation_suggestion":"Patentable. \"Systems and methods for improving address translation speed\" (US-8527736). https://patentable.app/patents/US-8527736","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8527736","json":"https://patentable.app/api/llm-context/US-8527736","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T17:15:24.548Z"}