{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8527802","patent":{"patent_number":"US-8527802","title":"Memory device data latency circuits and methods","assignee":null,"inventors":[],"filing_date":"2012-12-17T00:00:00.000Z","publication_date":"2013-09-03T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C"],"num_claims":18,"abstract":"A memory device can include a data path that includes a first-in-first-out circuit (FIFO) to transfer data according to a latency between at least one memory cell array and signal connections of the memory device, the latency corresponding to a number of cycles of a periodic clock; and a self-timed section configured to transfer data independent of the clock. In addition or alternatively, a memory device can include at least one memory cell array; and a FIFO configured to transfer data between at least one memory cell array and other portions of the memory device according to a periodic clock signal, FIFO introducing a latency into the data according to a control signal generated in response to an access command. Methods corresponding to the above devices and operations are also disclosed."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Memory device data latency circuits and methods","description":"A memory device can include a data path that includes a first-in-first-out circuit (FIFO) to transfer data according to a latency between at least one memory cell array and signal connections of the m","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8527802","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8527802","citation_suggestion":"Patentable. \"Memory device data latency circuits and methods\" (US-8527802). https://patentable.app/patents/US-8527802","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8527802","json":"https://patentable.app/api/llm-context/US-8527802","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T21:21:38.880Z"}