{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8530292","patent":{"patent_number":"US-8530292","title":"Method for manufacturing a strained channel MOS transistor","assignee":null,"inventors":[],"filing_date":"2011-09-09T00:00:00.000Z","publication_date":"2013-09-10T00:00:00.000Z","cpc_codes":["H01L","H01L"],"num_claims":17,"abstract":"A method for manufacturing a strained channel MOS transistor including the steps of: forming, at the surface of a semiconductor substrate, a MOS transistor comprising source and drain regions and an insulated sacrificial gate which partly extends over insulation areas surrounding the transistor; forming a layer of a dielectric material having its upper surface level with the upper surface of the sacrificial gate; removing the sacrificial gate; etching at least an upper portion of the exposed insulation areas to form trenches therein; filling the trenches with a material capable of applying a strain to the substrate; and forming, in the space left free by the sacrificial gate, an insulated MOS transistor gate."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method for manufacturing a strained channel MOS transistor","description":"A method for manufacturing a strained channel MOS transistor including the steps of: forming, at the surface of a semiconductor substrate, a MOS transistor comprising source and drain regions and an i","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8530292","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8530292","citation_suggestion":"Patentable. \"Method for manufacturing a strained channel MOS transistor\" (US-8530292). https://patentable.app/patents/US-8530292","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8530292","json":"https://patentable.app/api/llm-context/US-8530292","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T09:42:22.443Z"}