{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8530900","patent":{"patent_number":"US-8530900","title":"Method for selectively forming crystalline silicon layer regions above gate electrodes","assignee":null,"inventors":[],"filing_date":"2012-06-13T00:00:00.000Z","publication_date":"2013-09-10T00:00:00.000Z","cpc_codes":["H01L","H01L"],"num_claims":10,"abstract":"Preparing a substrate; forming a plurality of gate electrodes above the substrate; forming a gate insulating layer above the gate electrodes; forming an amorphous silicon layer above the gate insulating layer; forming crystalline silicon layer regions by irradiating the amorphous silicon layer in regions above the gate electrodes with a laser beam having a wavelength from 473 nm to 561 nm so as to crystallize the amorphous silicon layer in the regions above the gate electrodes, and forming an amorphous silicon layer region in a region other than the regions above the gate electrodes; and forming source electrodes and drain electrodes above the crystalline silicon layer regions are included, and a thickness of the gate insulating layer and a thickness of the amorphous silicon layer satisfy predetermined expressions."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method for selectively forming crystalline silicon layer regions above gate electrodes","description":"Preparing a substrate; forming a plurality of gate electrodes above the substrate; forming a gate insulating layer above the gate electrodes; forming an amorphous silicon layer above the gate insulati","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8530900","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8530900","citation_suggestion":"Patentable. \"Method for selectively forming crystalline silicon layer regions above gate electrodes\" (US-8530900). https://patentable.app/patents/US-8530900","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8530900","json":"https://patentable.app/api/llm-context/US-8530900","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T18:03:49.189Z"}