{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8530974","patent":{"patent_number":"US-8530974","title":"CMOS structure having multiple threshold voltage devices","assignee":null,"inventors":[],"filing_date":"2012-05-16T00:00:00.000Z","publication_date":"2013-09-10T00:00:00.000Z","cpc_codes":["H01L"],"num_claims":5,"abstract":"A complementary metal oxide semiconductor (CMOS) structure having multiple threshold voltage devices includes a first transistor device and a second transistor device formed on a semiconductor substrate. A set of vertical oxide spacers selectively formed for the first transistor device are in direct contact with a gate dielectric layer of the first transistor device such that the first transistor device has a shifted threshold voltage with respect to the second transistor device."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"CMOS structure having multiple threshold voltage devices","description":"A complementary metal oxide semiconductor (CMOS) structure having multiple threshold voltage devices includes a first transistor device and a second transistor device formed on a semiconductor substra","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8530974","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8530974","citation_suggestion":"Patentable. \"CMOS structure having multiple threshold voltage devices\" (US-8530974). https://patentable.app/patents/US-8530974","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8530974","json":"https://patentable.app/api/llm-context/US-8530974","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T13:42:27.213Z"}