{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8532163","patent":{"patent_number":"US-8532163","title":"Method and transceiver system having a transmit clock signal phase that is phase-locked with a receive clock signal phase","assignee":null,"inventors":[],"filing_date":"2012-02-06T00:00:00.000Z","publication_date":"2013-09-10T00:00:00.000Z","cpc_codes":["H04L","H04L"],"num_claims":20,"abstract":"A transceiver system is disclosed that includes a plurality of transceiver chips. Each transceiver chip includes one or more SERDES cores. Each SERDES core includes one or more SERDES lanes. Each SERDES lane includes a receive channel and a transmit channel. The transmit channel of each SERDES lane is phase-locked with a corresponding receive channel. The transceiver system has the capability of phase-locking a transmit clock signal phase of a transmitting component with a receive clock signal phase of a receiving component that is a part of a different SERDES lane, a different SERDES core, a different substrate, or even a different board. Each SERDES core receives and transmits data to and from external components connected to the SERDES core, such as hard disk drives. A method of transferring data from a first external component coupled to a receive channel to a second external component coupled to a transmit channel is also disclosed."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method and transceiver system having a transmit clock signal phase that is phase-locked with a receive clock signal phase","description":"A transceiver system is disclosed that includes a plurality of transceiver chips. Each transceiver chip includes one or more SERDES cores. Each SERDES core includes one or more SERDES lanes. Each SERD","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8532163","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8532163","citation_suggestion":"Patentable. \"Method and transceiver system having a transmit clock signal phase that is phase-locked with a receive clock signal phase\" (US-8532163). https://patentable.app/patents/US-8532163","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8532163","json":"https://patentable.app/api/llm-context/US-8532163","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T23:24:01.232Z"}