{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8533432","patent":{"patent_number":"US-8533432","title":"Cache and/or socket sensitive multi-processor cores breadth-first traversal","assignee":null,"inventors":[],"filing_date":"2012-09-27T00:00:00.000Z","publication_date":"2013-09-10T00:00:00.000Z","cpc_codes":["G06F"],"num_claims":35,"abstract":"Methods, apparatuses and storage device associated with cache and/or socket sensitive breadth-first iterative traversal of a graph by parallel threads, are described. A vertices visited array (VIS) may be employed to track graph vertices visited. VIS may be partitioned into VIS sub-arrays, taking into consideration cache sizes of LLC, to reduce likelihood of evictions. Potential boundary vertices arrays (PBV) may be employed to store potential boundary vertices for a next iteration, for vertices being visited in a current iteration. The number of PBV generated for each thread may take into consideration a number of sockets, over which the processor cores employed are distributed. The threads may be load balanced; further data locality awareness to reduce inter-socket communication may be considered, and/or lock-and-atomic free update operations may be employed."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Cache and/or socket sensitive multi-processor cores breadth-first traversal","description":"Methods, apparatuses and storage device associated with cache and/or socket sensitive breadth-first iterative traversal of a graph by parallel threads, are described. A vertices visited array (VIS) ma","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8533432","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8533432","citation_suggestion":"Patentable. \"Cache and/or socket sensitive multi-processor cores breadth-first traversal\" (US-8533432). https://patentable.app/patents/US-8533432","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8533432","json":"https://patentable.app/api/llm-context/US-8533432","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T18:03:02.290Z"}