{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8536043","patent":{"patent_number":"US-8536043","title":"Reduced S/D contact resistance of III-V MOSFET using low temperature metal-induced crystallization of n+ Ge","assignee":null,"inventors":[],"filing_date":"2011-01-31T00:00:00.000Z","publication_date":"2013-09-17T00:00:00.000Z","cpc_codes":["H01L","H01L"],"num_claims":21,"abstract":"Embodiments of this invention provide a method to fabricate an electrical contact. The method includes providing a substrate of a compound Group III-V semiconductor material having at least one electrically conducting doped region adjacent to a surface of the substrate. The method further includes fabricating the electrical contact to the at least one electrically conducting doped region by depositing a single crystal layer of germanium over the surface of the substrate so as to at least partially overlie the at least one electrically conducting doped region, converting the single crystal layer of germanium into a layer of amorphous germanium by implanting a dopant, forming a metal layer over exposed surfaces of the amorphous germanium layer, and performing a metal-induced crystallization (MIC) process on the amorphous germanium layer having the overlying metal layer to convert the amorphous germanium layer to a crystalline germanium layer and to activate the implanted dopant. The electrical contact can be a source or a drain contact of a transistor."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Reduced S/D contact resistance of III-V MOSFET using low temperature metal-induced crystallization of n+ Ge","description":"Embodiments of this invention provide a method to fabricate an electrical contact. The method includes providing a substrate of a compound Group III-V semiconductor material having at least one electr","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8536043","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8536043","citation_suggestion":"Patentable. \"Reduced S/D contact resistance of III-V MOSFET using low temperature metal-induced crystallization of n+ Ge\" (US-8536043). https://patentable.app/patents/US-8536043","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8536043","json":"https://patentable.app/api/llm-context/US-8536043","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T13:25:04.381Z"}