{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8536628","patent":{"patent_number":"US-8536628","title":"Integrated circuit having memory cell array including barriers, and method of manufacturing same","assignee":null,"inventors":[],"filing_date":"2008-11-11T00:00:00.000Z","publication_date":"2013-09-17T00:00:00.000Z","cpc_codes":["G11C","G11C"],"num_claims":18,"abstract":"An integrated circuit device (e.g., a logic device or a memory device) having (i) a memory cell array which includes a plurality of memory cells (for example, memory cells having electrically floating body transistors) arranged in a matrix of rows and columns, wherein each memory cell includes at least one transistor having a gate, gate dielectric and first, second and body regions, wherein: (i) the body region of each transistor is electrically floating and (ii) the transistors of adjacent memory cells include a layout that provides a common first region and/or a common second region. Each common first region and/or second regions of transistors of adjacent memory cells includes a barrier disposed therein and/or therebetween, wherein each barrier provides a discontinuity in the common regions and/or includes one or more electrical characteristics that are different from one or more corresponding electrical characteristics of the common regions. A plurality of electrical contacts, wherein an electrical contact is disposed on a (i) common first region and/or second region and (ii) barrier(s) associated therewith which is disposed therein and/or therebetween. Also disclosed are inventive methods of manufacturing such integrated circuit devices."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Integrated circuit having memory cell array including barriers, and method of manufacturing same","description":"An integrated circuit device (e.g., a logic device or a memory device) having (i) a memory cell array which includes a plurality of memory cells (for example, memory cells having electrically floating","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8536628","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8536628","citation_suggestion":"Patentable. \"Integrated circuit having memory cell array including barriers, and method of manufacturing same\" (US-8536628). https://patentable.app/patents/US-8536628","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8536628","json":"https://patentable.app/api/llm-context/US-8536628","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T13:19:34.257Z"}